1. Field of Invention
The present invention relates to semiconductor memory arrays, and more particularly to NAND arrays biased to reduce punchthrough.
2. Related Art
As semiconductor technology progresses, smaller and higher density chips are desired to accommodate the need for smaller and more powerful devices. One approach toward achieving this goal is to increase the integration density of semiconductor memories, such as EEPROMs, by reducing the physical dimensions of the EEPROM. One type of EEPROM designed to attain a high integration density is comprised of columns of NAND strings, each string having a plurality of memory cells with select transistors at the ends of each array, all of which are formed as one unit. The integration density of this type of EEPROM can be further increased by decreasing the channel length of individual memory cells or transistors comprising the NAND strings. However, if transistors such as MOSFETs are scaled down to channel lengths less than approximately 2 .mu.m, a problematic "short-channel" effect called punchthrough can arise.
Punchthrough is associated with the merging of source and drain depletion layers in the MOSFET, i.e., when the drain depletion layer extends across the substrate and reaches the source layer, thereby causing a destructive conduction path or leakage current between the source and drain. A drain depletion layer forms and spreads as the voltage applied across the transistor from the drain to the source (V.sub.DS) is increased. At a certain V.sub.DS called the punchthrough voltage, the width of the drain depletion layer approaches the spacing between the source and drain (i.e., the channel length), and the depletion regions meet, resulting in punchthrough. As MOSFET dimensions are scaled down, the channel length is reduced. Because channel length is reduced, the drain depletion layer reaches the source quicker as V.sub.DS is increased, resulting in punchthrough at lower drain/source voltages.
In MOSFETS with channel lengths greater than about 2 .mu.m, punchthrough is not a limiting factor for channel lengths. However, as channel lengths are shortened to the range of approximately 1-2 .mu.m, leakage currents through the drain of the MOSFETs occur at voltages below the avalanche-breakdown value to cause punchthrough. FIG. 1 shows a typical curve of the maximum drain voltage (with the source grounded) as a function of channel length. As seen, punchthrough is a serious problem in short-channel devices with a channel length less than about 2 .mu.m.
Therefore, the ability to scale down MOSFETs is limited by the punchthrough voltage. In other words, high drain/source voltages necessarily increase the minimum channel length of short-channel MOSFETS. As a result, reducing the channel length of transistors in the EEPROM is constrained due to high drain/source voltages needed for programming the EEPROM, which limits the amount that the EEPROM can be physically reduced.
Accordingly, an EEPROM is desired that can be scaled down with reduced punchthrough effects.